Tutorials Monday March 12, 2007
The tutorials take place in room ETZ F76.1 in the ETZ building.
- Haohuan Fu, Oskar Mencer and Wayne Luk, Imperial College London:
Optimizing Hardware Function Evaluation
Details
- Mateusz Majer, Diana Göhringer, Josef Angermeier and Jürgen Teich, University of Erlangen-Nuremberg:
The Erlangen Slot Machine: A run-time reconfigurable FPGA-based computer
for partially reconfigurable applications
Details
Schedule
Time |
Program |
08:30-10:30 |
The Erlangen Slot Machine, part I |
10:30-11:00 |
Coffee Break |
11:00-13:00 |
The Erlangen Slot Machine, part II |
13:00-14:00 |
Lunch |
14:00-15:30 |
Optimizing Hardware Function Evaluation, part I |
15:30-16:00 |
Coffee Break |
16:00-17:30 |
Optimizing Hardware Function Evaluation, part II |
Workshops Thursday March 15, 2007
The workshops take place in the ETZ building in rooms ETZ E6 (Dynamically reconfigurable systems) and ETZ E8 (Dependability and Fault Tolerance).
- A. Koch, Technical University Darmstadt and Ch. Hochberger, Technical University Dresden:
Dynamically Reconfigurable Systems
Details
- K.E. Grosspietsch, Fraunhofergesellschaft St. Augustin:
Dependability and Fault Tolerance
Details
Detailed Information
Tutorial: Optimizing Hardware Function Evaluation
Speakers: Haohuan Fu, Oskar Mencer, Wayne Luk
Location: room ETZ F76.1, ETZ building
Abstract
Many applications in multimedia, communications and finance involve
mathematical functions, such as exponential and trigonometric
functions. A good understanding of hardware function evaluation
enables selection and development of architectures for specific
requirements; such architectures typically make use of polynomials,
tables, shift-and-add, and various other techniques. The large number
of available methods leaves users with the task of deciding when to
use which method.
In this tutorial, we first present a methodology and an automated
system to decide which method to use, given range, precision, space,
and time considerations. We show how to select the best function
evaluation hardware for a given function, accuracy requirements,
technology mapping and optimization metrics, such as area,
throughput, and latency. Function evaluation f(x) typically
consists of range reduction, and the actual evaluation
on a small convenient interval such as [0, pi/2] for sin(x).
We outline the impact of hardware function evaluation with range
reduction for a given range and precision of x and f(x) on
area and speed. An automated bit-width optimization technique
for minimizing the size of operators in hardware datapaths is
also proposed. We illustrate design space exploration for
various fixed-point functions such as sin(x) and log(x) accurate
to one unit in the last place using MATLAB and ASC, A Stream
Compiler for Field-Programmable Gate Arrays (FPGAs).
As part of the function evaluation optimization challenge,
we extract bit-width optimization as an easily identifiable
subproblem with a wide variety of possible solutions. Bit-width
analysis can be done statically or dynamically. We show one method
for static bit-width analysis based on affine arithmetic, and one
method for dynamic bit-width analysis based on automatic
differentiation of sets of expressions.
The application of the methods presented in this tutorial
can be used to optimize hardware implementation at the
architecture level, the arithmetic level, and the bit level.
Speaker Biographies
Oskar Mencer
Oskar Mencer is an EPSRC Advanced Research Fellow and Senior
Lecturer at the Department of Computing at Imperial College London.
Prior to joining Imperial, Oskar was a Member of Technical Staff
in the Computing Sciences Center at Bell Labs in Murray Hill.
He got his PhD in Electrical Engineering in the Computer Architecture
and Arithmetic Group at Stanford University, and a B.Sc degree from
the Technion, Israel Institute of Technology. More information at:
http://www.doc.ic.ac.uk/~oskar
Wayne Luk
Wayne Luk, Professor of Computer Engineering at Imperial College
London, obtained his doctorate from Oxford University. He received
Best Paper Awards at International Conference on Field-Programmable
Logic and Applications in 2004, and at IEEE International Conference on
Field-Programmable Technology in 2005. His research interests include
theory and practice of customizing hardware and software for specific
application domains, such as multimedia, communications, and
finance. More information at: http://www.doc.ic.ac.uk/~wl
Tutorial: The Erlangen Slot Machine: A run-time reconfigurable FPGA-based computer for partially reconfigurable applications
Speakers: Mateusz Majer, Diana Göhringer, Josef Angermeier and Jürgen Teich
Location: room ETZ F76.1, ETZ building
Abstract
In this tutorial, we introduce an FPGA-based reconfigurable platform
called Erlangen Slot Machine (ESM) and tools supporting the
development of partially reconfigurable modules and their communication.
The main advantages of this platform in comparison to other platforms
are on one hand the possibility for each module to access peripherals,
such as video or audio in-and outputs, independent from its placement
through a programmable crossbar, and on the other hand local SRAM banks
for individual modules. With these advantages, the implementation of
run-time reconfigurable partial modules is easier and an unrestricted
relocation of modules on the device is possible.
The ESM consists of two boards called MotherBoard and BabyBoard. The
actual MotherBoard is designed for Multimedia applications. All
peripherals together with a PowerPC and an FPGA for the crossbar are
implemented on this board. The BabyBoard is application independent and
can therefore be mounted on different MotherBoards, depending on the
needs of the user. The main FPGA, in which the reconfigurable
applications run in so-called slots, is located on the BabyBoard. In
another FPGA next to it, the Reconfiguration Manager is located, that
reconfigures and relocates the modules on the main FPGA. For the
reconfiguration, the user just has to access the PowerPC on the
MotherBoard via the ESM-Shell, which then sends a command to the
Reconfiguration Manager. The PowerPC also is used to reprogram the
crossbar. A tool called SlotComposer helps the user to generate
partial bitstreams, by first inserting communication structures required
for partial reconfigurable designs, such as bus-macros, into VHDL files.
Secondly, scripts are generated to start the synthesis and to call the
EAPR-Flow tool offered by Xilinx.
During this tutorial we will demonstrate the functionality and
advantages of the ESM as a platform for partially reconfigurable
applications.
The tutorial will include the following:
- Introduction to platform and tools
- Partially reconfigurable module development using SlotComposer
- Reconfiguration Management
- Development of a reconfigurable video-filter application
Speaker Biographies
Mateusz Majer received his diploma degree (Dipl.-Ing.) in Electrical
Engineering from Darmstadt University of Technology, Germany, in October
2003. He is now in the final year of his PhD studies at the
Hardware/Software Co-Design Chair of the University of Erlangen-Nuremberg.
-
Diana Göhringer received her diploma degree (Dipl.-Ing.) in Electrical
Engineering and Information Technology from the University of
Karlsruhe(TH), Germany, in January 2006. She is now working as a PhD
student at the Hardware/Software Co-Design Chair of the University of
Erlangen-Nuremberg.
Josef Angermeier received his diploma degree (Dipl.-Inf.) in Computer
Science from University of Erlangen-Nuremberg, Germany, in December
2005. He is now working as a PhD student at the Hardware/Software
Co-Design Chair of the University of Erlangen-Nuremberg.
-
Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honors). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbrücken, Germany from where he received his PhD degree (summa cum laude). His PhD thesis entitled "A Compiler for Application-Specific Processor Arrays" summarizes his work on extending techniques for mapping computation intensive algorithms onto dedicated VLSI processor arrays. In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc). From 1995-1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zürich, Switzlerland, finishing his habilitation entitled "Synthesis and Optimization of Digital Hardware/ Software Systems" in 1996. From 1998-2002, he was full professor in the Electrical Engineering and Information Technology department of the University of Paderborn, Germany, holding a chair in Computer Engineering. In Paderborn he also worked in two Collaborative Research Centers sponsored by the German Science Foundation (DFG). Since 2003, he is appointed full professor in the Computer Science Institute of the University Erlangen-Nuremberg, holding the new chair in Hardware-Software-Co-Design.
Mr. Teich has been a member of multiple program committees of well-known conferences such as the DATE (Design, Automation, and Test in Europe) as well as editor of several books. Prof. Teich coordinates the German priority program 1148 (DFG) on reconfigurable computing. Since 2004, Prof. Teich is also elected reviewer of the German Research Foundation (DFG) for the area of Computer Architectures and Embedded Systems. His special interests are massive parallelism, embedded systems, hardware/software codesign, and computer architecture.
Workshop on "Dynamically Reconfigurable Systems (DRS)"
Chairs: A. Koch, Technical University Darmstadt and Ch. Hochberger, Technical University Dresden
Location: room ETZ E6, ETZ building
Schedule
Time |
Program |
9:00-10:00 |
Keynote 1: Dr. Juanjo Noguera, Xilinx Research Labs Europe: Application-driven research in partial reconfiguration abstract |
10:00-10:30 |
Coffee Break |
|
Architectures and Paradigms |
10:30-11:00 |
Yann Thoma, Andres Upegui, Andres Perez-Uribe, and Eduardo Sanchez (ReDS, HES-SO/HEIG-VD, Yverdon):
Self-Replication Mechanism by Means of Self-Reconfiguration
|
11:00-11:30 |
Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez (Univesité Pierre et Marie Curie, Paris):
Unifying Mesh and MFPGA architectures to improve performances
|
11:30-12:00 |
Peter Zipf, Lei Liu, Zdravko Bozakov, Manfred Glesner (Darmstadt University of Technology):
Design Optimisations for a Cellular Automata Model with Programmable
Interconnect Structure
|
|
Middleware |
12:00-12:30 |
Alessandro Cilardo, Luigi Coppolino, Nicola Mazzocca (University of Naples Federico II):
A framework for the Design of Distributed Reconfigurable Embedded Systems
|
12:30-13:00 |
Axel Schneider, Joachim Knäblein, Bernd Müller, Marcel Putsche (Alcatel-Lucent Germany), Sebastian Goller, Uwe Pross, Ulrich Heinkel (University of Technology Chemnitz):
Ethernet based in-service reconfiguration of SoCs in telecommunication networks
|
13:00-14:00 |
Lunch Break |
14:00-15:00 |
Keynote 2: Dr. Mladen Berekovic, IMEC: Reconfigurable Architectures in Embedded System-on-Chips |
15:00-15:30 |
Coffee Break |
|
Tools |
15:30-16:00 |
Sebastian Lange, Martin Middendorf (University of Leipzig):
Online Strategies for the Reconfiguration of Two-Level Reconfigurable Architectures
|
16:00-16:30 |
Markus Rullmann, Sebastian Siegel, Renate Merker (University of Technology Dresden), Julio A. Oliveira Filho, Thomas Schweizer, Tobias Oppold, Wolfgang Rosenstiel (University of Tübingen):
Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture
|
16:30-17:00 |
Sándor P. Fekete, Jan C. van der Veen (Braunschweig University of Technology), Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich (University of Erlangen-Nuremberg):
Scheduling and Communication-Aware Mapping of HW/SW Modules for Dynamically and Partially Reconfigurable SoC Architectures
|
Keynotes
-
Dr. Juanjo Noguera, Xilinx Research Labs Europe: Application-driven research in partial reconfiguration
Partial Reconfiguration (PR) is a unique feature of Xilinx FPGA's that
allows the reconfiguration of a part of the device while the rest of the FPGA
continues operating. This approach, where the application functionality is
time-multiplexed on the FPGA has been widely addressed by many researchers in
academia, proposing multiple architectures and techniques for hardware
virtualization but without a clear focus on the application perspective. The
main goal of this talk is to propose a change in the current approach. Thus, we
believe that applications or application domains, and not architectures, should
drive the research in partial reconfiguration. Using this application-focussed
view of partial reconfiguration, we introduce the need for high-level
domain-specific design tools that enable the users to specify the behaviour of
the application and how the system should react to changes in its environment.
Several examples using the networking domain will be provided.
Workshop on "Dependability and Fault Tolerance"
Chair: K.E. Grosspietsch, Fraunhofergesellschaft St. Augustin
Location: room ETZ E8, ETZ building
Schedule
Time |
Program |
09:00-09:10 |
Welcome |
09:10-10:00 |
Invited Talk: K. Echtle (University of Duisburg-Essen):
Fault-Tolerant Communication in Safety-Relevant Automotive Applications
|
10:00-10:30 |
Coffee Break |
|
Hardware Fault Tolerance |
10:30-11:00 |
R. Kothe, H.T. Vierhaus (University of Technology Cottbus):
Repair Functions and Redundancy Management for Bus Structures
|
11:00-11:30 |
B. Fechner, J. Keller (Fernuniveristät Hagen):
Compression-free Checksum-based Fault-Detection Schemes for Pipelined Processors
|
|
Dependable Mechatronic Systems |
11:30-12:00 |
F. Mösch, M. Litza, A. El Sayed Auf, B. Jakimovski, E. Maehle (University of Lübeck),
W. Brockmann (University of Osnabrück):
Organic Fault-Tolerant Controller for the Walking Robot OSCAR
|
12:00-12:30 |
R. Agarwal (Envirotech Instruments Pvt. Ltd, New Delhi), K.-E. Grosspietsch (Fraunhofer-Gesellschaft, St. Augustin):
Fault Tolerance for Autonomous Robots by Means of Adaptive Filters
|
12:30-13:00 |
D. Dötz, H. Hoffmann, D. Scherer, C. Trinitis, M. Walter (Technische Universität München):
On the Automation of Incremental Metal Forming Processes
|
13:00-14:00 |
Lunch Break |
|
Modeling and Simulation of Dependable Systems |
14:00-14:30 |
P. Limbourg, H.-D. Kochs, K. Echtle, I. Eusgeld (University of Duisburg-Essen)
Reliability Prediction in Systems with Correlated Component Failures —
An Approach Using Copulas
|
14:30-15:00 |
M. Walter, C. Trinitis (Technische Universität München):
Automatic Generation of State-Based Dependability Models: from Availability to Safety
|
14:30-15:00 |
P. Gawkowski, J. Sosnowski (Warsaw University of Technology):
Experiences with Software Implemented Fault Injection
|
15:00-15:30 |
F. Belli, C.J. Budnik (Universität Paderborn):
Elementare Mutations-Operatoren zur Generierung von Testfällen anhand von Statecharts
|
16:00-16:30 |
Coffee Break |
|
Modeling and Simulation of Dependable Systems |
16:30-17:00 |
F. Saglietti, N. Oster, F. Pinte (University Erlangen-Nuremberg):
Interface Coverage Criteria Supporting Model-Based Integration Testing
|
17:00-17:30 |
F. Belli, M. Linschulte (Universitüt Paderborn), I. Schieferdecker (Technische Universität Berlin):
Ereignisorientiertes Testen Web-basierter Systeme — Verfeinerung des holistischen Ansatzes und eine Fallstudie
|
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